Optoelectronic –VLSI technology aims at presuming the integration of photonic devices with VLSI. We hereby examine the discrepancy of VLSI technology with conventional wire-bonded Opto-electronics packaging .The outcomes shows that the integration provides stuff power and faster even when small numbers of photonic devices are driven with commodity complementary metal–oxide–semiconductor logic technologies. Using this technology we can interface optical information and circuits with VLSI in a single package.
Optoelectronic -VLSI technology provides close integration of photonic devices with VLSI electronics .
It’s theme is to supply multiple high-performance optical inputs and output signals, with aggregate data-rates up to and even exceeding a terabit-per-second, to state-of-the-art VLSI circuits. OE-VLSI technologies are used most effectively in systems where a high-bandwidth “data-firehose” must be received, switched or quickly processed by the electronic circuit, and communicated out of the subsystem. Such a technology allows a significant increase in integration density over all-electrical systems because the functionality present in many separate electronic chips can be condensed into fewer chips with large numbers of optical inputs and/or outputs (I/O’s).
The use of OE-VLSI “packaging” simultaneously affords a reduction in the energy required to transmit digital signals within the system by reducing the parasitics associated with conventional packaging technology that use wire-bonds between chips. This permits an increase in interconnect speed for a given power dissipation. We will review emerging OE-VLSI technologies, and in the subsequent sections we will quantify the benefits of intimately integrating the photonic devices to the VLSI circuits by comparing an OEVLSI technology to a more conventional packaging approach where the photonic devices are wire-bonded to the electronics.
“Smart-pixel” technologies can employ materials with widely differing properties for light detection, logic, and optical transmission .Smart pixels are mostly based on either silicon or gallium arsenide substrates. The main logic families are silicon CMOS, silicon bipolar, and GaAs MESFET’s. Optical I/O channel being associated with only a specific subset of transistors on the chip is replaced with a more comprehensive view of a technology that provides surface-normal optical interconnects to VLSI circuits through either monolithic or hybrid integration methods. OE-VLSI technology can be expected provide an I/O bandwidth to a chip that grows in proportion to its computational bandwidth, even for ultradense CMOS VLSI. Three approaches are presently under investigation: laser sources, LED sources, and light modulators. The first approach has the advantage that active light sources such as vertical-cavity surface-emitting lasers (VCSEL’s) can provide large dynamic range and high contrast ratios. Light-emitting diodes (LED’s) can presently be integrated
on a large scale with GaAs logic and also with silicon. They benefit from simpler fabrication and larger tolerance to processing variations, but suffer from higher on-chip power dissipation and smaller modulation bandwidth. The light-modulator approach has the advantage that modulator
fabrication processes can be extremely simple and may be more consistent with logic technology. They are capable of being produced in large arrays with high-yields. Light modulators are high-impedance, capacitive devices (much like a CMOS gate) and hence can reduce the onchip dissipated power. For high-speed digital interconnectionS the multiple-quantumwell (MQW) electroabsorption (EA) modulator can be used. This is a low-capacitance device that can be switched at gigabits-persecond data rates by standard CMOS circuits.
The most widely used means of providing electrical connections between electronic driver or receiver circuits and optical devices such as modulators and lasers, is wire-bonding. A short-wire bond can provide a simple and cost effective means of connecting the photonic devices to the
transceivers electronics. It is generally believed that the number of wire-bonds that will be possible to a single electronic chip, and the necessary on-chip electrical routing to the wire bond pads, will ultimately limit the electrical I/O to a VLSI circuit. But it is the precise performance tradeoffs between
wire-bonding and flip-chip bonding of OE’s to VLSI that is the subject of this paper. There are some more works like comparing the optical interconnects to off-chip electrical interconnects at the chip-to-chip and levels. The off-chip electrical interconnects are assumed to be treated as purely capacitive lumped loads. Here, the objective is to quantify the tradeoff between
the speed and the power-dissipation of a wire-bonded OE transceiver versus corresponding flip-chip bonded OE-VLSI
transceiver. Assuming the line parameters and the load characteristics of the OE output device in each case are known. The outcome of this can be used to determine the power-speed tradeoffs of onchip versus off-chip optical transceivers and to quantify the benefits of intimate integration of optical transceivers onto VLSI electronics.
The integration of photo detectors and emitters into the single package subsystem is achieved by a silicon microminiature optical assembly (OMA), which couples a photo emitter or detector to an optical fiber and provides an electrical contact pad for the photo device to interface with receiver/driver ICs. This OMA is solder bonded to the substrate and makes electrical contact to mating pads on the substrate. The OMA is batch fabricated using standard silicon. The process involves double-sided non-planar photolithography and anisotropic wet etching. A 4′ silicon wafer typically contains 500 OMAs. Each OMA measures
approximately 2 mm x 2 mm. The OMA contains an etched well on the bottom.surface and a through aperture extending between the top surface and the well. A photo detector or emitter is then placed in the well with the active side making contact with the bottom of the well and the active area centered over the through aperture. Electrical contact to the photo device is made by a conductive contact between the photo device and the well, and a wire bond to the back side of the device. The conduction path from the photo device is
extended up the walls of the well to a series of solder bumps, which are then connected to the substrate structure in a flipchip bonding operation. The metalization is accomplished by non-planar photolithography using an inorganic photoresist. Insertion of an optical fiber is performed during the final steps of assembly. The separation between the fiber and the optoelectronic device can be controlled by the dimension of the aperture, and the fiber can be secured by epoxy or mechanical means. Strain relief of the fiber is provided by the package. The optical fiber extends from the OMA in the direction normal to the plane of the substrate. An alternative design of the OMA that contains an additional etched v-grwve and reflector could provide a parallel fiber arrangement.
In this paper, we briefly reviewed the motivations and status of emerging OE-VLSI technologies. All the OE-VLSI
integration techniques reviewed in this paper have the common goal of providing dense integration of OE devices to VLSI circuit
with minimum electrical parasitics, i.e., low capacitance ,resistance and inductance. The purpose of the remainder of the paper was to compare the performance of such an OE-VLSI device to that of a conventional wire-bonded OE circuit. Specifically, we have attempted to quantify the power-speed
benefits of a hybrid flip-chip bonded OE-VLSI technology to a low-cost, wire-bonded OE packaging technique as a function of array size. To do this, we examined the behavior of a simple series-terminated transmission line where the source resistance is not perfectly matched to the line-impedance, but instead is designed to minimize power dissipation at the expense of a controlled amount of signal-degradation due to ringing. The specific values for the parasitics that were assumed for the OE VLSI technology was based on recent measurements of flip-chip bonded MQW modulators on CMOS, although the results in general are relevant to all intimate integration techniques that provide low-parasitic interconnections to single, linear, or 2-D arrays of photonic devices. It is important to note that efforts to extract high-speed performance from conventional wire-bond packaging technology will necessitate the use of very-low-resistance drivers and end-terminated (matched) transmission lines. These high performance packaging techniques are not those typically associated with high-volume electronics, but are instead the purview of special-purpose logic technologies and microwave packaging.